The present invention generally relates to a level conversion circuit for converting an ECL (Emitter Coupled Logic) level signal into a TTL (Transistor-Transistor Logic) level signal. The present invention is suitable for a level conversion circuit provided in a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) memory such as BiCMOS-ECL SRAM (Static Random Access Memory).
There is known a BiCMOS SRAM having a level conversion circuit and a TTL-level internal logic circuit. An ECL-level input signal is input to the level conversion circuit, which converts the ECL-level input signal into a TTL-level signal. The converted TTL-level signal is input to the TTL-level internal logic circuit. In order to increase the operating speed of such a memory, it is necessary to increase the operating speed of the level conversion circuit.
Referring to FIG. 1, there is illustrated an ECL gate circuit 1 and a level conversion circuit 2. The ECL gate circuit 1 is made up of five bipolar transistors Tr1-Tr5. An input signal is subjected to a level shift operation by the transistor Tr1. The transistors Tr2 and Tr3 form a differential switch circuit. A reference volta V.sub.R is always applied to the base of the transistor Tr3. When a low-level input signal is applied to an input terminal A connected to the base of the transistor Tr1, the transistor Tr3 is turned ON. On the other hand, when a high-level input signal is applied to the input terminal A, the transistor Tr2 is turned ON and the transistor Tr3 is turned OFF.
Thus, when the high-level signal is applied to the input terminal A, the transistor Tr4 outputs a low-level signal and the transistor Tr5 outputs a high-level signal. When the low-level signal is applied to the input terminal A, the output signals of the transistors Tr4 and Tr5 are inverted.
The output signals from the ECL gate circuit 1 are input to the level conversion circuit 2, which are composed of P-channel MOS transistors Tr6, Tr8, Tr10 and Tr12 and N-channel MOS transistors Tr7, Tr9, Tr11 and Tr13. When the transistors Tr4 and Tr5 of the ECL gate circuit 1 output the low-level signal and the high-level signal, respectively, the transistors Tr8 and Tr10 are turned ON, and the transistors Tr6 and Tr12 are turned OFF. When the transistor Tr6 is turned OFF, the transistors Tr7 and Tr9 are also turned OFF. Thus, a high-level output signal from the level conversion circuit 2 is applied to a buffer gate 3a having a BiCMOS inverter. Thus, the buffer gate 3a generates an output signal Q at a low-level.
When the transistor Tr10 is turned ON, the transistors Tr11 and Tr13 are also turned ON. Thus, a low-level output signal from the level conversion circuit 2 is applied to a buffer gate 3b having a BiCMOS inverter. Thus, the buffer gate 3b outputs an output signal Q having a high level. Thus, the output signal Q from the buffer gate 3b has the logic value opposite to that of the input signal A, and the output signal Q has the logic value identical to that of the input signal A.
The output signals from the ECL gate circuit 1 are all input to the P-channel MOS transistors Tr6, Tr8, Tr10 and Tr12. This is due to the fact that the output signals from the ECL gate circuit 1 are not sufficient to drive N-channel MOS transistors because of the difference in characteristics of the P-channel MOS transistors and the N-channel MOS transistors in the level conversion circuit 2. The output signals from the ECL gate circuit 1 are input directly to the P-channel MOS transistors Tr8 and Tr12 which drive the buffer gates 3a and 3b. On the other hand, the N-channel MOS transistors Tr9 and Tr13 which drive the buffer gates 3a and 3b are driven through the P-channel MOS transistors Tr6, Tr7, Tr10 and Tr11.
The level conversion circuit 2 does not have a load driveability sufficient to drive a large number of internal circuits. For this reason, the buffer gates 3a and 3b are interposed between the level conversion circuit 2 and internal circuits (not shown) processing TTL-level signals so that a load driveability sufficient to the internal circuits is attained.
FIG. 2 shows a detained structure of the buffer gates 3a and 3b. The buffer gate 3a is composed of MOS transistors Tr14 and Tr15 which form an input stage thereof, and bipolar transistors Tr18 and Tr19 which form an output stage thereof. Similarly, the buffer gate 3b is composed of MOS transistors Tr16 and Tr17 and bipolar transistors Tr20 and Tr21.
The output signals from the ECL gate circuit 1 are supplied to the internal circuits through the level conversion circuit 2 and the buffer gates 3a and 3b. Thus, it takes a long time to execute the level conversion from the ECL level into the TTL level so that the operation speed of the level conversion is not high. For example, the low-level signal is applied to the transistor Tr6, and the transistors Tr7 and Tr9 are turned ON and thereafter the low-level signal is input to the buffer gate 3a. Thus it takes a time amounting to three stages of transistors to obtain the high-level output signal from the buffer gate 3a. Further, it takes the operating time of the buffer gate 3a to supply the internal circuits with the output signal of the buffer gate 3a.
It is considered to increase the load driveability of the level conversion circuit 2 so that the buffer gates 3a and 3b are omitted. In order to realize such an arrangement, it is necessary to increase the dimension of each transistor in the level conversion circuit 2. This leads to a decrease in the integration level.
FIG. 3 shows waveforms obtained at nodes (a) through (i) shown in FIG. 1 when the ECL-level input signal applied to the input terminal A changes from the low level to the high level. The low level of the input signal is approximately -1.7 volts, and the high level thereof is approximately -0.9 volts. The TTL-level output signal Q from the buffer gate 3a shown in FIG. 3-(h) is changed from the high level to the low level. The high level of the output signal from the buffer gate 3a is approximately 0.4 volts and the low level thereof is approximately -0.4 volts. As shown in FIG. 3-(i), the TTL-level output signal Q is changed from the low level to the high level. The delay time it takes to convert the ECL level into the TTL-level is approximately 1.8 ns.